1. Field
The embodiments discussed herein relate to memory devices used for computation processing equipment and information equipment.
2. Description of Related Art
Memories can be broadly divided into RAMs (random access memories) and ROMs (read only memories). The RAMs are volatile memories and the ROMs are nonvolatile memories.
Further, the RAMs are broadly grouped into SRAMs (static RAMs, which do not involve memory retention operation) and DRAMs (dynamic RAMs, which involve memory retention operation, such as refreshing).
The SRAMs feature high-speed read/write access (which is about ten times faster than DRAMs) and the DRAMs feature to have the capability to have increased capacities. Thus, typically, the DRAMs are used as main memories and the SRAMs are used as primary storage memories. With recent improvements in the processing speeds, attempts have been made to reduce the access time of the SRAMs and the DRAMs.
The read/write speeds of the SRAMs and DRAMs are determined by the data rates of interfaces for the memories. Thus, as the data rates, there are an SDR (single data rate) at which a trigger occurs at the rising edge of a clock signal, a DDR (double data rate) at which a trigger occurs at the falling edge of the clock signal in addition to the rising edge of the clock signal, and a QDR (quad data rate) at which a trigger occurs at both the rising edge and the falling edge of the clock signal, with an input port and an output port being separated from each other.
FIG. 1 illustrates the configuration of a known memory device. The known memory device includes an SDR-SDRAM 1, a DDR-SDRAM 2, and a QDR-SRAM 3. The SDR-SDRAM 1, the DDR-SDRAM 2, and the QDR-SRAM 3 include corresponding interfaces 1A to 3A and corresponding memory chips 1B to 3B and are coupled to a CPU (central processing unit) and an input/output device (e.g., a keyboard and a monitor) through a data bus.
Voltages of 1.8 V, 2.5 V, and 5.0 V are supplied from a power source to the interfaces 1A, 2A, and 3A, respectively. A clock signal and an address signal are input to the interfaces 1A to 3A through the data bus, so that input/output (read/write) of data is performed.
The SDR-SDRAM 1 is mainly used as a memory that does not involve high-speed processing, the DDR-SDRAM 2 is mainly used as a main memory having a large capacity, and the QDR-SRAM 3 is mainly used as a primary storage memory that involves high speed processing.
Thus, the known memory device includes memory chips and interfaces for the corresponding data rates. Additionally, voltage values used by the interfaces are different from each other.
The SDR-SDRAM 1, the DDR-SDRAM 2, and the QDR-SRAM 3 are selectively used depending on the application of computation processing equipment or information equipment, its processing capability, or the like, and in some cases, an SDR-SRAM is also used instead of the SDR-SDRAM 1.